A small fully digital open-loop clock and data recovery circuit for wired BANs
نویسندگان
چکیده
منابع مشابه
A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit
A 4Gb/s power and area efficient clock/data recovery (CDR) circuit is proposed. Fully-differential design is employed to reject any common mode noises and to significantly reduce power/ground bounce. An analog dual delay-locked loop (DLL) architecture continuously aligns the clock sampling edge to the center of incoming data eye-opening. A self-correcting function prevents the phase capture ran...
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ژورنال
عنوان ژورنال: International Journal of Circuit Theory and Applications
سال: 2015
ISSN: 0098-9886
DOI: 10.1002/cta.2092